This invention relates to integrated circuits and, more particularly, to fixing errors in already fabricated integrated circuit designs, or in integrated circuits with significant portions thereof being outside the bounds of redesign efforts.
Some present day designs of integrated circuits (ICs) comprise a plurality of module, or core, designs (and associated designed layouts) that are interconnected within the integrated circuit to create a whole. Such ICs are sometimes referred to as “systems on a chip” (SoCs). The designed SoCs may include core designs that the party designing the integrated circuit has created before, core designs purchased from another party, and core designs created specifically for the subject integrated circuit, sometimes is referred to as user defined logic (UDL) blocks.
The aforementioned Ser. No. 10/425,101 patent application discloses a beneficial design approach for SoCs, where each core is encompassed with a wrapper that includes functionally reconfigurable module (FRM). A wrapper is a collection of elements, which collection includes a circuit interface between essentially every input terminal of the core and circuitry outside the core, and between essentially every output terminal of the core and circuitry outside the core. The FRM can be configurably connected to any of the circuit interfaces, and inherently also can be configured to realize any function. Spare leads between wrappers are disclosed, which enable connectivity from an FRM directly to circuitry outside the wrapper. The circuitry outside the core can be another wrapper, a UDL block, inputs of the IC, or outputs of the IC.
FIG. 1 depicts an arrangement in accord with the disclosure presented in the aforementioned Ser. No. 10/425,101 patent application, where an SoC includes core 10 that is wrapped by wrapper 11, core 20 that is wrapped by wrapper 21, and core 30 (a UDL block) that is wrapped by wrapper 31. Illustratively, core 10 has three inputs and four outputs (12, 13, 14, and 15). Core 20 has four inputs, three outputs (22, 23, and 24) that are needed for the SoC design, and one output (25) that is available, but is not needed for the FIG. 1 SoC design. In the original design, 25 was an internal signal of core 20, and 25 has been made available to be processed by the wrapper 21. UDL 30 has three inputs and two outputs (32, and 33) that are connected to the SoC output terminals of the IC. In addition to the necessary signal connections between wrappers 11 and 21, and between wrappers 21 and 31, including spare leads, the FIG. 1 SoC includes manager circuit 40 through which control is exercised over the SoC. It accepts a system clock, a test clock, a control signal, and information through Scan-in input 41. This information is injected into the Scan-in (SI) input of wrapper 11. The Scan-out (SO) output of wrapper 11 is connected to the SI input of wrapper 21, the SO output of wrapper 21 is connected to the SI input of wrapper 31, and the SO output of wrapper 31 is connected to a terminal of the SoC. Input 41 and the daisy chain connection of the SI and SO leads of the wrappers as described above allows the installation of configuration information for the wrappers, and entry of information into all of the flip-flops within wrappers 11, 21, and 31, as well is within cores 10, 20, and 30. The SO output 42 provides for outputting the states of the flip-flops within cores 10, 20, and 30 via circuit 40. Of course, other embodiments are possible, where, for example, there is a separate path for scanning in and out the flip-flops within the cores, and for scanning in and out the flip-flops within the FRMs.
All ICs go through an extensive pre-silicon design verification process that attempts to find as many errors as possible before the IC is manufactured. Nevertheless, about two thirds of the newly fabricated chips have errors that are discovered during the first silicon debug stage. Currently, errors in silicon can be corrected only by remanufacturing the IC. This, of course, is an expensive process. It is also time consuming, often taking several months to complete.